1. Field of the Invention
The present invention relates in general to a method for forming a non-volatile memory cell. More particularly, it relates to a method for forming a vertical nitride read-only memory (NROM) cell.
2. Description of the Related Art
The non-volatile memory industry began development of nitride read-only memory (NROM) in 1996. This relatively new non-volatile memory technology utilizes oxide-nitride-oxide (ONO) gate dielectric and known mechanisms of program and erase to create two separate bits per cell. Thus, the NROM bit size is half of the cell area. Since silicon die size is the main element in the cost structure, it is apparent why the NROM technology is an economic breakthrough.
FIG. 1 is a cross-section showing a conventional NROM cell structure. This cell includes a silicon substrate 100 which has two separated bit lines (source and drain) 102, two bit line oxides 104 formed over each of the bit lines 102, respectively, and an ONO layer 112 having a silicon nitride layer 108 sandwiched between the bottom silicon oxide layer 106 and the top silicon oxide layer 110 formed on the substrate 100 between the bit line oxides 102. A gate conductive layer 114 (word line) lies on the top of the bit line oxides 104 and the ONO layer 112.
The silicon nitride layer 108 in the ONO structure 112 has two chargeable areas 107 and 109 adjacent to the bit lines 102. These areas 107 and 109 are used for storing charges during memory cell programming. To program the left bit close to area 107, left bit line 102 is the drain and receives the high programming voltage. At the same time, right bit line 102 is the source and is grounded. The opposite is true for programming area 109. Moreover, each bit is read in a direction opposite its programming direction. To read the left bit, stored in area 107, left bit line 102 is the source and right bit line 102 is the drain. The opposite is true for reading the right bit, stored in area 109. In addition, the bits are erased in the same direction that they are programmed.
Increasing cell density for integration of ICs requires shrinking the width of the ONO layer. Unfortunately, shrinking the gate length (the width of the ONO layer) may induce cell disturbance during programming, erasing, or reading, in particular, when width of the gate length is less than 10 nm. Therefore, the cell density is limited.
Accordingly, an object of the present invention is to provide a novel method for forming a vertical nitride read-only memory (NROM) cell, which uses the formation of a vertical channel instead of the conventional planar one, thereby preventing cell disturbance during programming, erasing, and reading.
According to the object of the invention, the invention provides a vertical NROM cell, which includes a substrate, a source line, a first doping region, an insulating layer, a second doping region, a gate dielectric layer, and a control gate. The substrate has at least one trench. The source line is disposed in the lower trench and insulated from the substrate. The first doping region is formed in the substrate adjacent to the top of the source line and the second doping region is formed in the substrate adjacent to the top of the trench. The insulating layer is disposed on the source line. The control gate is disposed in the upper trench and insulated from the substrate by the gate dielectric layer disposed over the sidewall of the trench and on the insulating layer.
Moreover, the source line and control gate can be doped polysilicon layers. The gate dielectric layer can be an oxide-nitride-oxide (ONO) layer.
Additionally according to the object of the invention, the invention provides a method for forming a vertical NROM cell. First, a substrate having at least one trench is provided. Next, a first conductive layer is formed in the lower trench and insulated from the substrate to serve as a source line. A doped insulating layer is then formed over the sidewall of the middle trench and on the first conductive layer, and then a drive-in treatment is performed on the doped insulating layer to form a first doping region in the substrate adjacent to the top of the first conductive layer. Thereafter, the doped insulating layer is removed. Next, a first insulating layer is formed on the first conductive layer. Next, a second doping region is formed in the substrate adjacent to the top of the trench. Next, a second insulating layer is formed over the sidewall of the trench and on the first insulating layer to serve as a gate dielectric layer. Finally, a second conductive layer is formed in the upper trench to serve as a control gate.
Additionally, the first and second conductive layers can be doped polysilicon layers.
The doped insulating layer can be an arsenic silicate glass (ASG) layer and has a thickness of about 100-200 xc3x85. The drive-in treatment can be performed at 900-1100xc2x0 C. for 20-40 min.
Moreover, the first insulating layer can be a silicon oxide layer and the second insulating layer can be an oxide-nitride-oxide layer.